On-Chip Inductance in High Speed Integrated Circuits
(Sprache: Englisch)
The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated...
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The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies. On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively.
On-Chip Inductance in High Speed Integrated Circuitsis full of design and analysis techniques for RLC interconnect. These
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techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance.
On-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.
On-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.
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Inhaltsverzeichnis zu „On-Chip Inductance in High Speed Integrated Circuits “
1 Introduction.- 2 Basic Transmission Line Theory.- 2.1 Transmission Lines.- 2.2 Approximate Models for RC Interconnect.- 2.3 Repeater Insertion in RC Lines.- 3 Evaluating The Transient Response of Linear Networks.- 3.1 Elmore Delay and Wyatt Approximation.- 3.2 Higher Order Transient Response Approximations Using Moment Matching Techniques.- 4 Misfit Current-Voltage Characteristics.- 4.1 Basic Theory of Operation of a MOSFET.- 4.2 Alpha Power Law Model for Short Channel Devices.- 5 Figures of Merit to Characterize the Importance of on-Chip Inductance in Single Lines.- 5.1 Theoretical Analysis of Inductance Effects in RLC Interconnect.- 5.2 Range of Interconnect for Significant Inductance Effects.- 5.3 Conclusions.- 6 Effects of Inductance on the Propagation Delay and Repeater Insertion Process in RLC Lines.- 6.1 Propagation Delay of a Gate Driving an RLC Load.- 6.2 Repeater Insertion for an RLCInterconnect.- 6.3 Conclusions.- 7 Equivalent Elmore Delay for RLC Trees.- 7.1 Second Order Approximation for RLC Trees.- 7.2 Signal Characterization in RLC Trees for a Step Input.- 7.3 Accuracy Characterization of the Second Order Approximation.- 7.4 Conclusions.- 8 Characterizing Inductance EFFECTS in RLC Trees.- 8.1 Effect of Damping Factor and Input Rise Time.- 8.2 Results and Examples.- 8.3 Conclusions.- 9 Repeater Insertion in Tree Structured Inductive Interconnect.- 9.1 Algorithm for Repeater Insertion in RLC Trees.- 9.2 Delay Model.- 9.3 Results and Discussion.- 9.4 Summary.- 10 Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.- 10.1 Capacitive Approximation of a Lossless Transmission Line.- 10.2 Dynamic and Short-Circuit Power.- 10.3 Conclusions.- 11 Exploiting on-Chip Inductance in High speed Clock Distribution Networks.- 11.1 Useful Inductance Effects.- 11.2 Clock Distribution Network Example.- 11.3 Summary.- 12 Accurate and Efficient Evaluation of The Transient Response in RLC Circuits: the DTT Method.- 12.1 The DTT Method.- 12.2
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Complexity and Stability of the DTT Method.- 12.3 Experimental Results.- 12.4 Conclusions.- 13 on the Extraction of On-Chip Inductance.- 13.1 Characteristics of On-Chip Inductance which Simplify the Extraction Process.- 13.2 Summary.- 14 Conclusions.- Appendix B - Optimum Repeater Insertion in RLC Lines.- Appendix C - Complexity of the Equivalent Elmore Delay Model.- Appendix D - Matching Conditions of A CMOS Gate Driving a Lossless Transmission Line.- Appendix E - the DTT Algorithm.- Appendix F - Comparison between DTT and Awe.- About the Authors.
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Autoren-Porträt von Yehea I. Ismail, Eby G. Friedman
Professor Dr. Eby Friedman, Department of Electrical & Computer Engineering, University of Rochester, Rochester, New York 14627-0231, USA.
Bibliographische Angaben
- Autoren: Yehea I. Ismail , Eby G. Friedman
- 2012, Softcover reprint of the original 1st ed. 2001, XXII, 303 Seiten, Maße: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1461356776
- ISBN-13: 9781461356776
Sprache:
Englisch
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