Low Power Networks-on-Chip
(Sprache: Englisch)
With power consumption now a key design constraint, recent years have seen growing research interest in these networks as an architectural solution for high-speed data transfer. This single-source reference covers some of the most important design techniques.
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With power consumption now a key design constraint, recent years have seen growing research interest in these networks as an architectural solution for high-speed data transfer. This single-source reference covers some of the most important design techniques.
Klappentext zu „Low Power Networks-on-Chip “
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Inhaltsverzeichnis zu „Low Power Networks-on-Chip “
- Network-on-Chip Power Estimation- Timing
- synchronous/asynchronous communication
- Network-on-Chip link design
- Topology exploration
- Network-on-Chip support for CMP/MPSoCs
- Network design for 3D stacked logic and memory
- Beyond the wired Network-on-Chip
Bibliographische Angaben
- 2014, 2011, 287 Seiten, Maße: 15,4 x 23,4 cm, Kartoniert (TB), Englisch
- Herausgegeben: Cristina Silvano, Marcello Lajolo, Gianluca Palermo
- Verlag: Springer, Berlin
- ISBN-10: 1489994378
- ISBN-13: 9781489994370
Sprache:
Englisch
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