CAD for Hardware Security
(Sprache: Englisch)
This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC...
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This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC verification experts. Readers will gain a comprehensive understanding of SoC security vulnerabilities and how to overcome them, through an efficient combination of proactive countermeasures and a wide variety of CAD solutions.
Inhaltsverzeichnis zu „CAD for Hardware Security “
Introduction.- CAD for Information Leakage Assessment.- CAD for Power Side Channel Leakage Assessment.- CAD for Electromagnetic Radiation Leakage Assessment.- CAD for Timing Leakage Assessment.- CAD for Fault Injection Attack Analysis.- CAD for Obfuscation.- CAD for Watermarking.- CAD for HW Metering.- CAD for Detecting HLS Vulnerabilities.- CAD for Counterfeit Detection and Prevention.- CAD for Trojan Detection and Prevention.- CAD for Physical Assurance.- CAD for Anti-Probing.- CAD for Formal Security Verification.- CAD for Reverse Engineering.
Autoren-Porträt von Farimah Farahmandi, M. Sazadur Rahman, Sree Ranjani Rajendran, Mark Tehranipoor
Farimah Farahmandi is an assistant professor in the Department of Electrical and Computer Engineering (ECE) and the associate director of Edaptive Computing Inc., Transition Center (ECI-TC), and Florida Institue for Cybersecurity (FICS) at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering (CISE) at the University of Florida, 2018. Her research interests include hardware security verification, formal methods, fault-injection attack analysis, side-channel leakage assessment, information leakage, secure physical design, secure supply chain of microelectronics, and post-silicon validation and debug. Her research has resulted in five books, nine book chapters, and several publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including 2022 Semiconductor Research Corporation Young Faculty Award and the 2022 ECE Research Excellence Award at UF. She is also the recipient of four best paper nominations from IEEE/ACM ASPDAC and IEEE/ACM DATE as well as IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, and DAC Richard Newton Young Student Fellowship. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Currently, she is the program chair of IEEE HOST 2023. Her research has been sponsored by SRC, DARPA, AFRL, DoD, ONR, Analog Devices, ANSYS, Synopsys, and Cisco. She is a member of IEEE and ACM.M Sazadur Rahman a Security Assurance architecture Engineer at Intel Corporation. He earned his M.Sc. and Ph.D. degree under the supervision of Prof. Mark Tehranipoor from University
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ofFlorida in 2022. He got his B.Sc. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology in 2014. He worked as a design engineer in different fabless semiconductor companies from 2014 to 2017 in industrial scale 28nm and 14nm custom ICs. His research has resulted in one book, multiple patents, and several peer-reviewed publications in premier ACM/IEEE journals and conferences, including the Design Automation Conference (DAC), Design automation and test in Europe (DATE), IEEE International Test Conference (ITC), IEEE Hardware Oriented Security and Trust (HOST), IEEE VLSI Test symposium (VTS), Elsevier Integration, ACM Transactions on Design Automation of Electronic Systems (TODAES), etc. He has multiple internship experiences at Intel Corporation, where he performed FIPS 140-3 security certification and developed an automated threat model review tool for different adversary models. His research interest includes IP protection and authentication, logic locking, security estimation, and CAD for security.
Sree Ranjani Rajendran is a postdoctoral associate in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Electronics and Communication Engineering at the Amrita Vishwa Vidyapeetham in 2019. She received her B.E. and M.E. from the Department of Electronics and Communication Engineering at Anna University, sIndia, in 2007 and 2012.Her research interests include hardware security verification and validation of System-on-Chips. Her research has been published in premier ACM/IEEE journals and conferences, including IEEE Transactions on Emerging Topics in Computing, Journal of Cryptographic Engineering, ACM Workshop on Attacks and Solutions in Hardware Security, International Conference on VLSI Design & The International Conference on Embedded Design, and Design Automation and Test in Europe (DATE). She is a member of IEEE andT
Sree Ranjani Rajendran is a postdoctoral associate in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Electronics and Communication Engineering at the Amrita Vishwa Vidyapeetham in 2019. She received her B.E. and M.E. from the Department of Electronics and Communication Engineering at Anna University, sIndia, in 2007 and 2012.Her research interests include hardware security verification and validation of System-on-Chips. Her research has been published in premier ACM/IEEE journals and conferences, including IEEE Transactions on Emerging Topics in Computing, Journal of Cryptographic Engineering, ACM Workshop on Attacks and Solutions in Hardware Security, International Conference on VLSI Design & The International Conference on Embedded Design, and Design Automation and Test in Europe (DATE). She is a member of IEEE andT
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Bibliographische Angaben
- Autoren: Farimah Farahmandi , M. Sazadur Rahman , Sree Ranjani Rajendran , Mark Tehranipoor
- 2024, 2023, XVIII, 407 Seiten, Maße: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 3031268989
- ISBN-13: 9783031268984
Sprache:
Englisch
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